Recently the storage capacity of a magnetic recording/reproducing unit or optical recording/reproducing unit is rapidly increasing as the information volume to be handled increases, therefore it is necessary to increase recording density. However the increase of recording density deteriorates the data quality, so recently a system called the PRML (Partial Response Maximum Likelihood) signal processing method is used to guarantee reliability. This system has a high reproducing performance even for high density recording/reproducing waveforms. The PRML signal processing method is a method for improving the error rate of the reproducing data in a reproducing system, in which the amplitude of the high frequency component of the signal deteriorates and the signal-noise ratio increases as the recording density in the line recording direction increases, and by also using the maximum likelihood decoding method, which makes it unnecessary to use a high frequency component in the reproducing signals by intentionally adding waveform interference, and which demodulates the most likely series by probability calculation considering the waveform interference.
PR of the PRML signal processing method is for intentionally adding waveform interference, and is a processing that filters so as to match the PR type of the system. The configuration that is often used for equalization (filtering) to the PR type is that after pre-equalization with an analog filter, further adjustment is made by a post-digital adaptive filter. However equalization to the PR by the analog filter may shift due to an irregularity of the recording medium. The post-digital adaptive filter decreases the influence by the equalization shift of the pre-equalization by adaptive equalization.
ML of the PRML signal processing method is a maximum likelihood signal, of which characteristic can be improved when there is a correlation among the decoder input signal series, and which is used for decoding the most likely data. In PRML, the characteristic is improved by PR since there is a correlation among the decoder input signal series. The above ML is a synchronization circuit, so clock signals synchronizing with the reproducing signals are required. In the reproducing signal of the disk device, however, the frequency changes somewhat because of an unevenness of the rotation of the spindle motor. To follow up this change, a circuit called a PLL (Phase Locked Loop) is required.
Among those systems using the PRML signal processing method and PLL, a system using a digital PLL, based on interpolation, is currently on the market. If this system is used, the number of analog components can be decreased. Also the analog-digital converter is not in the PLL loop, so the loop delay of the PLL does not increase even if a pre-filter is inserted between the analog-digital converter and the PLL, and performance can be improved. Since the analog component of a PLL is unnecessary, and a system can be constructed by almost all digital circuits, the irregularity problem of analog circuits can be solved (e.g. JP10-27435A, pages 4-7, see FIG. 1 ).
In the system using the digital PLL, the pre-filter is constructed by a digital filter, so the characteristic of the digital filter can be freely changed by setting the factor thereof. Therefore the reproducing signal at the point of pre-equalization can have the desired frequency characteristic, and the frequency characteristic at which the performance of the PLL is the maximum can be implemented in the pre-stage of the PLL.
FIG. 8 shows a configuration example for implementing the adaptation of this pre-filter. The adaptation is performed as follows. In FIG. 8, the digital PLL using interpolation is the phase synchronization means 103. Using this phase synchronization means 103, the input/output signals of the first digital equalization means 102, that is the pre-filter, are both resampled and phases thereof are synchronized. The output signals of the first digital equalization means 102 are resampled by the first interpolation means 1031, and the input signals of the first digital equalization means 102 passes through a “delay”, and are resampled by the A/D conversion information interpolation means 801. Using these resampled input/output signals of the first digital equalization means 102, the tap factors of the first digital equalization means 102 are computed by the temporary factor computation means 802. Here the first digital equalization means 102 and the temporary factor computation means 802 are the computation means that operate at a different frequency, at frequency A and frequency B for example, so the tap factors acquired by the temporary factor computation means 802 are fed back to the first digital equalization means 102 via the rate converter 803, that converts the frequency. By using this rate converter 803, the adaptive control of the pre-filter becomes possible (e.g. JP2001-184795A, pages 6-9, see FIG. 1).
However in the case of the above system, if the difference of the sampling frequency of the analog-digital converter and the resampling frequency of the PLL is large, the burden on the rate converter 803, which converts the rate of the tap factors, is high, and high order interpolation is required onboard the rate converter 803 to maintain performance, which makes the circuit scale large.
For example, if the data is read from a disk medium where the data is recorded with a constant line recording density by a CAV (Constant Angular Velocity) method, the data frequencies to be read are quite different between the inner tracks and outer tracks. But in the case of the above mentioned system using the digital PLL, the sampling frequency of the analog-digital converter is fairly constant. The digital PLL executes resampling so as to roughly synchronize with the data frequency. In the case of this example, the ratio of the sampling frequency of the analog-digital converter and the resampling frequency of the PLL changes in the range of double or more, so the rate converter 803 requires a performance which can sustain these changes.
Also in this system, the sampling frequency of the analog-digital converter is higher than the resampling frequency of the PLL. In digital signal processing, the accuracy of the computation improves as computation is performed at a higher frequency, but the tap factor computation of the pre-filter is performed at a low frequency, that is with the signals after resampling, so computation accuracy cannot be improved.